Digital Drosophila Archive
4.7 KiB
Persistent-process engineering replay — 2026-10-01
User authorized continuing performance optimization after the exact V100 eligibility prototype. This is a NEW bounded engineering experiment, not a resumption, retry, or extension of the stopped scientific Phase4AR run. No future assay, learning run, game or decoder is authorized here.
Immutable inputs and selection
- Original registration SHA256:
b63e6281b6505ca3b60acb467dd0b3fae274cf513dcbfd653649ba52e9ba9740. - Original scientific source commit:
80aeb2093db655329774eff7b32fb6e417b8b40b. - Prior exact-GPU replay code commit:
221e1f13f758ebe8d9f188bab976c361f7cacf45. - Fixed real fixture manifest:
/home/qishizhe/phase4ar-v100-acceleration-20261001/fixtures/manifest.json. - Fixture manifest SHA256:
481df128d39bf28e5984a6f2e5757f83d45cb7a6136f8d2843ecc0a67eca437b. - Use all14 fixtures in their existing order: first and last committed task by task-ID within7arms, chosen in the prior experiment without reading outcomes. Coverage is only the available committed prefix, not the complete scientific design.
- All anatomical data, sources, saved requests, before-overlay, historical checkpoint and original update references remain read-only. No new update is installed. No request/RNG regeneration, learning-rate, sign, threshold, timestep or eligibility change.
CPU lanes
Measure original U in fresh processes and separate resident producer/verifier processes. The verifier owns independently loaded inputs and invokes unchanged original U recomputation. This measures update-interface overhead, NOT full AQ authority/checkpoint verification. Use3 fixed passes; all outputs/receipts must match the original CPU oracle.
Also measure unchanged original E.postprocess_epoch in a resident CPU process,2 fixed passes, new output per call. Preserve all checks inside E. Original full AQ validation remains a fresh CPU subprocess; never bypass its fresh-interpreter guards. Profile function costs separately; profiler-instrumented timings are not speed benchmarks.
Brain lanes
Use only the original scientific environment and admitted RTX4090 for this pass. Original Torch lacks V100 support for its frozen whole-brain runtime; V100 eligibility compatibility does not establish whole-brain compatibility.
Run unchanged R.run_light and original checkpoint seal/read functions. Baseline:14 fresh child processes. Candidate: one resident child executes14 forward then14 reverse. Every call creates a fresh neuronal/APL state through the unmodified function. No use of checkpoint continuation, old BrainRuntime, custom state reset, or previous effective-weight accumulation. This first pass reuses interpreter, verified module caches, CUDA context, and the runtime's existing caches only; it does not cache GPU graph tensors or rewrite the numerical loop.
Compare every event, counts, final v/g/ref, spike ring, APL state/pending/phase, effective-weight hash and request acceptance against the historical sealed trial. Check exact dtypes, shapes and bytes. Verify source/input pins before and after trials. Failures stop the affected lane and retain evidence; no selection of passing trials.
Audit, timing and bounds
Each resident job has a completion record but NOT a fictitious OS exit code. Its session receives an independently observed actual process exit only when the whole child exits. No old AR ledger is modified.
Report initialization/compilation, immutable-input authentication, execution, checkpoint seal/read, comparison, output I/O and complete child wall times separately. Report data transfer, recording and checks that remain. Independent stage measurements cannot be added and advertised as a measured end-to-end training speedup; no new full-run ETA from isolated kernels.
Run CPU and GPU timing lanes serially to avoid artificial contention. Check all3 ComfyUI queues before each GPU trial; no service eviction. Maximum engineering workflow30minutes, each child15minutes, new artifacts capped at2GiB and100GiB minimum free disk reserve. If an infrastructure or candidate bug occurs, preserve the attempt and correct only new source/attempt paths; never retry scientific AR tasks.
Outputs: /home/qishizhe/phase4ar-pipeline-acceleration-20261001/. Source: new conditioning-pipeline-acceleration-v1 directory in independent worktree /home/qishizhe/digital-drosophila-v100-acceleration.
Pre/post checks: original saved64,034-file Phase4AR inventory,16 registered sources, previous acceleration artifact manifest and previous acceleration source hashes. This is NOT a new Phase1–4AQ numerical regression.
Possible gate: PASS-PERSISTENT-REPLAY-EQUIVALENCE for tested lanes only. It is not a learned-model candidate, formal production-runtime promotion, full scientific-gate pass, or permission to resume30,000epochs.