Seal Phase4AF exact short fullgraph author GPU gate and APL integration audit

2026-09-30 08:14:16 +08:00
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+# Phase 4AF: full-graph author numerical gate
+
+The independent branch is authorized by the human; frozen models are not replaced.
+Use the complete canonical 166,700-neuron/25,582,938-edge graph, every original
+integer synaptic-contact count, the frozen source transmitter signs and W_syn
+0.275 mV/contact. Do not remove isolates, self-loops or any existing edge.
+
+Float64 is the unmodified author's default, not a precision chosen for activity.
+The archived original create_model, Brian2 2.5.1/NumPy1.22.3 and its actual scalar
+coefficients define the oracle. Use unchanged Phase4AE CUDA math as read-only
+dependency, not an approximate solver. Initial state is v=-52mV, g=0, available;
+all cells retain the original 22-tick refractory rule and delay is exactly18ticks.
+The common deterministic stimulus requests v=threshold+1mV at before_thresholds
+only if not refractory. This is not original poi and not physiological input.
+
+Preregister three cases: no request for10ms; neuron1381 requested once at tick0
+for50ms; [1197,1381,1511,82312,133666] requested once at tick0 for50ms.
+Each CPU case uses one fresh process, zero-time compilation then one continuous
+nonzero Network.run. Full end-of-tick V/g/ref are streamed to .npy memory maps;
+spikes remain sparse events. GPU compares every tick bitwise against these maps.
+No dense spike matrix, no conditioning, no learning and no APL overlay in this
+isolated numerical gate. The omission of APL is explicit, not a revised calibrated
+brain. Any later APL branch integration requires its own semantic gate.
+
+Observe the actual Brian queue by forwarding the original peek result unchanged.
+SHA-256 per tick records raw original edge order and the original postsynaptic
+not_refractory acceptance mask. GPU digests the source-ordered expansion before
+stable target grouping. Joint hash has the versioned protocol header, little-endian
+tick/count, contiguous little-endian int64 IDs followed by uint8 accepted flags.
+Different targets may be scheduled in parallel, but each target's accumulation
+order and exact incoming old g are preserved. No separate reduction changes.
+
+Compare sparse event sequence, counts, every V/g bit, refractory, request
+accepted/rejected and queue edge/guard digests. Stop after the first failed trial;
+preserve a failure diagnostic, do not widen tolerance, choose alternate input or
+interpret low activity as success. Resource stops are incomplete, not scientific
+FAILs. New output budget15GiB; stream states and do not dump all arrivals.
+
+Before and after: verify original frozen inventory, subsequent AA--AE seals and
+the background evidence seal. Re-run the five old deterministic-v2 reference trials
+into this experiment only. These historical regressions do not certify new model
+learning or long-run equivalence. Record source hashes, graph/input hashes,
+environment, generated code, code commit, wall time and diagnostic peak VRAM.
+All outputs and source are sealed with manifests and SHA-256 after completion.